TouchLine station microprocessor, version 0161

Overwiew

General

The microprocessor is a Motorola 68HC05C4 mask programmed processor. It operates in different modes in stations with display and stations without display. The processor decides its operating mode by reading the pin PB0 after reset. If it is 0, the processor starts the display mode, if it is 1, the processor selects the non-display mode.

New features in the revised version 0159 are indicated by italics.

Display mode

In a station with display, the processor scans the keyboard every 10 ms and processes data received from the serial line. The processor is in the WAIT state between messages and scans to conserve power. The processor can scan up to 60 keys. The processor will signal the key by generating the digit tone and selecting the right ab loop current. All signalling is held for a minimum time even if the key is released to ensure that the exchange is able to receive it properly. In the display station, the M-key, C-key and Handset Off current levels are also controlled by the processor.

There is also options for scanning of a matrix keyboards, either in normal mode or in MICOM mode. M- and C-keys are then included in the scanned keyboard matrix.

The processor can output received data to a LCD display. It can also output data on the SPI port. The processor can set or reset an output line that is used to override handset off/volume setting. In addition, one extra output can be set or reset, alternatively set with timeout. This is primarily intended for door opening.

Non-display mode

In a station without display, the processor is in STOP condition when no key is pressed. The processor is started by a depressed key and continues to run until the last key is signalled to the exchange. The processor generates the digit tone and selects M-key current if necessary. The digit tone and current are held for a minimum time even if the key is released. In non-display mode, the processor can scan 40 keys.

There is also options for scanning of a matrix keyboards, either in normal mode or in MICOM mode. M- and C-keys are then included in the scanned keyboard matrix.

Pin usage

Display mode

The pins are used as follows:

Pin Name	Description
RESET	This is the reset input, the watchdog is connected to this input.
OSC1,<br\>OSC2	A 2.45MHz ceramic resonator is connected to these two pins. <br\>
VCC	The pin is connected to +5V.
GND	The pin is connected to 0V.
IRQ	The pin is not used and should be connected to +5V.
PA0..PA7	This 8 bit port is used as bi-directional data bus with the display. It is also used as address bus when data is shifted out on the SPI output.
PB0	At start-up, this input should read 0 to indicate that the processor should start display mode. Afterwards, it is used as E signal for the display.
PB1	R/W* signal for the display.
PB2	A0 signal for the display.
PB3	Common line for all digit only keys. The output is taken low when digit only keys are scanned. In matrix keyboard mode, this is row address 3.
PB4<br\><br\><br\>	Common line for digit + current keys. The output is taken low when digit + current keys are scanned. When data has been shifted out on the SPI, it is latched by taking both PB3 and PB4 low. Since PB3 and PB4 may be shorted together if more than one key is pressed, PB3 and PB4 should be buffered in circuits using the SPI output. In matrix keyboard mode, this is row address 2.
PB5	Handset and volume override. This output may be set to 1 or 0 by a command from the exchange. It is normally used to override handset off and volume control.
PB6	Handset off input. 5V at input indicates handset off.
PB7	ID control. Set to 1 while a digit is being sent.
PC0	Key no. 8 input. Used as output to latch data into external shift registers when scanning keys. If 0V at reset, matrix keyboard mode is selected.
PC1	Key no. 9 input. In matrix keyboard mode, this is an output, row address 1.
PC2	OPEN/PRIVATE switch input. 5v at input means OPEN.
PC3	M-key input. 0V at input means key pressed. In matrix keyboard mode, MICOM mode is selected if 0V at reset.
PC4	C-key input. 0V at input means key pressed. In matrix keyboard mode, this is an output, row address 4.
PC5	Handset current control. Taken low when either handset is off or handset off current is used together with digit.
PC6	M-key current control. Set high when either M-key is pressed or m-key current is used with digit.
PC7	C-key current control. Set high when either C-key is pressed or as a speed-up for m-key current.
PD0/RDI	Serial data input from exchange. 9600 baud, 8 bit data, 2 bit stop, no parity.
PD1/TDO	Serial data output. Data from the exchange may be transmitted here. 9600 baud, 8 bit data, 2 bit stop, no parity. This pin can also be used as an output pin controlled by commands 0x26, 0x27,0x28, and 0x29
PD2/MISO	Synchronous data input used to read key scan from external shift register.
PD3/MOSI	Synchronous data output. Data from the exchange may be shifted out on this output. After shifting, data is latched into external registers by taking both PB3 and PB4 low. The address is available on PA0..PA7 while strobing.
PD4/SCK	Clock output for synchronous input/output. Can be used to toggle watchdog.
PD5/SS*	Must be tied to 5V.
PD7	cd-loop polarity sense input. 5V at input signals c-wire negative.
TCAP	Not used, should be tied to 0 or 5V.
TCMP	OPEN/PRIVATE current control and digit tone output. Square wave output of digit tone when sending digit, else 1 when in PRIVATE and 0 in OPEN.

Non-Display mode

The pins are used as follows:

Pin Name	Description
RESET	This is the reset input, the reset circuit is connected to this input.
OSC1,<br\> OSC2	A 2.45MHz ceramic resonator is connected to these two pins. <br\>
VCC	The pin is connected to +5V.
GND	The pin is connected to 0V.
IRQ	The input is used to wake the processor if a key is pressed while the processor is in STOP condition.
PA0..PA7	Inputs for key 0 .. key 7. Input at 0V means key pressed. In matrix keyboard mode, they are column 1-8 inputs.
PB0	At start-up, this input should read 1 to indicate that the processor should start non-display mode.
PB1	Not used. Tie to 0V or 5V. In matrix keyboard mode, it is used to activate private to supply extra current to the processor while a key is depressed.
PB2	Output that is turned on to 5V when processor is running. Used to ensure that open keys reads as open. In three-state when processor is in STOP condition.
PB3	Common line for all digit only keys. The output is taken low when digit only keys are scanned. In matrix keyboard mode, it is used as row 4 output.
PB4	Common line for digit + current keys. The output is taken low when digit + current keys are scanned. In matrix keyboard mode, it is used as row 3 output.
PB5	Not used, tie to 0V or 5V. If 0V at reset, matrix keyboard mode is selected.
PB6	Not used, tie to 0V or 5V. If 0V at reset, and matrix keyboard mode is selected, MICOM mode keyboard is selected.
PB7	ID control. Set to 1 while a digit is being sent.
PC0	Key no. 8 input. In matrix keyboard mode, it is used as row 1 output.
PC1	Key no. 9 input. In matrix keyboard mode, it is used as row 2 output.
PC2..PC5	Key no. 16 .. key no. 19 input. Not used in matrix keyboard mode, and must be tied to 5V.
PC6	M-key current control. Set high when m-key current is used with digit.
PC7	Not used. Tie to 0V or 5V. In matrix keyboard mode, it is set high when C-key is pressed, and activates C-key current.
PD0..PD5	Key no. 10 .. key no. 15 input. Not used in matrix keyboard mode, and must be tied to 5V.
TCAP	Not used. Tie to 0V or 5V.
TCMP	Digit tone output. Square wave output of digit tone when sending digit.

Electrical operation

Keyboard scanning in display mode

The keyboard is a 2 x 30 switch matrix, giving two columns of 30 keys that is scanned one column at a time. The processor always scans 30 keys, but keys may be disabled by ensuring that they read as logic 1. The first column is selected by taking the PB3 pin low. The two first keys are read by reading level at the pins PC0 and PC1. Then the PC0 pin is made an output and taken high then low to latch the rest of the keys into external shift registers. The PB3 pin is taken high and the data in the external shift registers is shifted in through the processor's SPI port using the SCK output as clock. The clock is 306 kHz. After the keys has been decoded internally, the process is repeated for the second column, selecting the second column by taking PB4 pin low.

If an error is detected during scanning, that is, more than one key pressed at a time, the scanning may be aborted. An exception is M- and C-key in matrix keyboard mode.

The keys are placed as follows in the matrix:

Pin	Name with PB3 low	Name with PB4 low
PC0 on processor	Digit 8	M + Digit 8
PC1 on processor	Digit 9	M + Digit 9
1. pin shifted in	Digit 7	M + Digit 7
2. pin shifted in	Digit 6	M + Digit 6
3. pin shifted in	Digit 5	M + Digit 5
4. pin shifted in	Digit 4	M + Digit 4
5. pin shifted in	Digit 3	M + Digit 3
6. pin shifted in	Digit 2	M + Digit 2
7. pin shifted in	Digit 1	M + Digit 1
8. pin shifted in	Digit 0	M + Digit 0
9. pin shifted in	Digit 19	M + Digit 19
10. pin shifted in	Digit 18	M + Digit 18
11. pin shifted in	Digit 17	M + Digit 17
12. pin shifted in	Digit 16	M + Digit 16
13. pin shifted in	Digit 15	M + Digit 15
14. pin shifted in	Digit 14	M + Digit 14
15. pin shifted in	Digit 13	M + Digit 13
16. pin shifted in	Digit 12	M + Digit 12
17. pin shifted in	Digit 11	M + Digit 11
18. pin shifted in	Digit 10	M + Digit 10
19. pin shifted in	Handset Off + Digit 9	Handset Off + Digit 19
20. pin shifted in	Handset Off + Digit 8	Handset Off + Digit 18
21. pin shifted in	Handset Off + Digit 7	Handset Off + Digit 17
22. pin shifted in	Handset Off + Digit 6	Handset Off + Digit 16
23. pin shifted in	Handset Off + Digit 5	Handset Off + Digit 15
24. pin shifted in	Handset Off + Digit 4	Handset Off + Digit 14
25. pin shifted in	Handset Off + Digit 3	Handset Off + Digit 13
26. pin shifted in	Handset Off + Digit 2	Handset Off + Digit 12
27. pin shifted in	Handset Off + Digit 1	Handset Off + Digit 11
28. pin shifted in	Handset Off + Digit 0	Handset Off + Digit 10

If PC0 (KB8) is 0V at reset, matrix keyboard mode is entered. PC3 (MKEY) is used to select between normal and MICOM keyboard types. PC1 (KB9) is used as row 1 address, PB4 (KEY+M) is used as row 2 address, PB3 (KEY-) is used as row 3 address, and PC4 (CKEY) is used as row 4 address. Separate M- and C-keys must not be used. The keys in the matrix is then defined in the following way (H indicates handset off): <br\><br\><br\><br\> PC0=0V, PC3=5V at reset

Signal	KB0	KB1	KB2	KB3	KB4	KB5	KB6	KB7
PC1	1	2	3	M+8	H+0	H+2	H+4	H+6
PB4	4	5	6	M+9	H+1	H+3	H+5	H+7
PB3	7	8	9	M+0	M+2	M+4	M+6	H+8
PC4	M	0	C	M+1	M+3	M+5	M+7	H+9

<br\><br\><br\><br\><br\><br\><br\> Keyboard type 1, standard keyboard plus 20 function keys <br\><br\><br\><br\> PC0=0V, PC3=0V at reset

Signal	KB0	KB1	KB2	KB3	KB4	KB5	KB6	KB7
PC1	1	2	3	M+8	H+0	H+2	H+4	H+6
PB4	4	5	6	M+9	H+1	H+3	H+5	H+7
PB3	7	8	9	M+0	M+2	M+4	M+6	H+8
PC4	0	M	C	M+1	M+3	M+5	M+7	H+9

<br\><br\><br\><br\><br\><br\><br\> Keyboard type 2, MICOM plus 20 function keys

Keyboard scanning in non-display mode

The keyboard is a 2 x 20 switch matrix, giving two columns of 20 keys that is scanned one column at a time. The processor always scans 20 keys, but keys may be disabled by ensuring that they read as logic 1. The first column is selected by taking the PB3 pin low. The keys are then read from processor input ports. PB3 is taken high and the keys are decoded internally. The process is repeated for the second column, selecting the second column by taking PB4 pin low.

The processor is in STOP condition when all keys have been signalled. It is started by pulling the IRQ pin low. The PB2 pin, which is three-state while the processor is in STOP condition, is made an high output when the processor is started. This may be used to disable further interrupts going into the IRQ pin.

If an error is detected during scanning, that is, more than one key pressed at a time, the scanning may be aborted. An exception is M- and C-key in matrix keyboard mode.

The keys are placed as follows in the matrix:

Pin	Name with PB3 low	Name with PB4 low
PC1	Digit 9	M + Digit 9
PC0	Digit 8	M + Digit 8
PA7	Digit 7	M + Digit 7
PA6	Digit 6	M + Digit 6
PA5	Digit 5	M + Digit 5
PA4	Digit 4	M + Digit 4
PA3	Digit 3	M + Digit 3
PA2	Digit 2	M + Digit 2
PA1	Digit 1	M + Digit 1
PA0	Digit 0	M + Digit 0
PD0	Digit 10	M + Digit 10
PD1	Digit 11	M + Digit 11
PD2	Digit 12	M + Digit 12
PD3	Digit 13	M + Digit 13
PD4	Digit 14	M + Digit 14
PD5	Digit 15	M + Digit 15
PC2	Digit 16	M + Digit 16
PC3	Digit 17	M + Digit 17
PC4	Digit 18	M + Digit 18
PC5	Digit 19	M + Digit 19

If PB5 is 0V at reset, matrix keyboard mode is entered. PB6 is used to select between normal and MICOM keyboard types. PC0 (KB8) is used as row 1 address, PC1 (KB9) is used as row 2 address, PB4 (KEY+M) is used as row 3 address, and PB3 (KEY-) is used as row 4 address. PB1 is used to activate private mode, to increase available current to the processor while a key is depressed. PC7 is used as an output to activate C-current. The keys in the matrix is then defined in the following way:

<br\><br\><br\><br\> PB5=0V, PB6=5V at reset

Signal	PA0	PA1	PA2	PA3	PA4	PA5	PA6	PA7
PC0	1	2	3	M+8	10	12	14	16
PC1	4	5	6	M+9	11	13	15	17
PB4	7	8	9	M+0	M+2	M+4	M+6	M+8
PB3	M	0	C	M+1	M+3	M+5	M+7	M+9

<br\><br\><br\><br\><br\><br\><br\> Keyboard type 1, standard keyboard plus 20 function keys <br\><br\><br\><br\> PB5=0V, PB6=0V at reset

Signal	PA0	PA1	PA2	PA3	PA4	PA5	PA6	PA7
PC0	1	2	3	M+8	10	12	14	16
PC1	4	5	6	M+9	11	13	15	17
PB4	7	8	9	M+0	M+2	M+4	M+6	M+8
PC3	0	M	C	M+1	M+3	M+5	M+7	M+9

<br\><br\><br\><br\><br\><br\><br\> Keyboard type 2, MICOM plus 20 function keys

Signalling on ab loop in display mode

The processor has three output lines that control ab loop current. PC5 pin controls handset on current, PC6 controls M-key current and PC7 controls C-key current. Only one of the outputs is on at a time in steady state. During transition from one current state to another however, more outputs may for a short time (some tens of milliseconds) be turned on or off to speed up reception of new current level in the exchange.

Signalling on ab loop in non-display mode

In non-display mode, the processor controls M-key current only through the PC6 pin. All speed-up must be done externally. In matrix keyboard mode, C-key current is controlled via PC7.

Signalling on cd loop

The PB7 pin is set high whenever the processor sends a digit tone. This signal is used to increase the cd loop current if c-wire is negative, else it is used to reduce the cd loop current. Then, on the TCMP pin, a square wave appears that has a frequency corresponding to the key that is being sent. See end of "Serial data commands, addresses and format" chapter for what frequencies go with what keys. On the ab loop, the current level may be changed to signal the key. When not sending keys, in non-display mode both pins is low. In display mode when not sending keys, the TCMP pin reflects the state of the OPEN/PRIVATE switch, being high if switch is in PRIVATE position. In non-display mode, when matrix keyboard mode is selected, private mode is activated via PB1 while a key is depressed.

Data output on SPI

Many of the data commands that the processor receives directs it to output data to external addresses. The data byte is then shifted out on the SPI output with the most significant bit first. The SCK signal is the shift clock, data is output on the rising edge and should be latched externally on the falling edge. After a whole byte has been shifted out, the address to which the byte should be written is output to PA0 .. PA7. Then pin PB3 and pin PB4 are pulsed low simultaneously to latch the byte.

PB3 and PB4 are normally used for keyboard scanning and may be shorted together if more than one key is pressed. In order to avoid false latching when using SPI data output, the PB3 and PB4 pins should have diodes in series or be buffered before being used in the keyboard.

Serial data commands, addresses and format

General

The microprocessor receives messages on the asynchronous serial input. First, the message is checked for errors in transmission using the checksum. Then the processor decides whether the message is addressed to this station. Last the data bytes in the message are sent to the display, the synchronous output, the asynchronous output or as digits back to the exchange, depending on the command type.

Serial format

The serial format is 8 bit, no parity, 2 stop bits, 9600 baud.

Message format

The message consists of the following items:

• A start of record mark, one byte. Always 0xa5.
• Byte count. One byte giving the number of bytes in the rest of the record. The count starts at the next byte and includes the checksum byte at the end of the record.
• Address. Two bytes telling for who this record is intended. The most significant byte comes first.
• Command type. One byte telling what the message is about.
• Data. Up to 18 bytes of data.
• Checksum. One byte checksum of record, obtained by adding count byte, address bytes, command byte and data bytes, ignoring any carry.

Addresses

The processor has three different address registers that it tries to match against the address of the incoming message:

• The 16 bit main address register that is loaded by a message. The register may be loaded by a message that requires a double pulse on the PD7 pin. The signal on PD7 is the polarity of the cd wire. The register is set to 0xff00 after reset, if RAM consistency check finds errors.
• The 8 bit K-group address register that can be loaded by a message. The register is cleared after reset, if RAM consistency check finds errors.
• The 8 bit short address register that can be loaded from port A (PA0..PA7). The short address can not be used together with the standard LCD module as a load from port A will then read from the controller in the display. The register is cleared after reset, if RAM consistency check finds errors.

<br\><br\> The address range of the incoming messages is divided as follows:

Address	Interpretation
0x0000 - 0xfbff	The address is compared directly with the 16 bit main address register.
0xfc00 - 0xfcff	The lower 8 bits are compared with the short address register.
0xfd00 - 0xfdff	The lower 8 bits are compared with the K-group address register.
0xfe00 - 0xfeff	The lower 8 bits are compared with the upper 8 bits of the main address register. The processor have 0xff00 in the main address register after reset so that 0xfeff is group broadcast to all processors whose main address register is not yet loaded.
0xfffe	Maskable broadcast to all processors.
0xffff	Unmaskable broadcast to all processors.

Commands

The command byte tell the processor what to do. Command 1, 2 and 3 requires that a standard LCD module is connected to the processor.

Command	Action description
0x01	Write data in message to low address (control register of display). Wait for display to become ready for each byte.